Design of Low-Leakage CNTFET SRAM Cell at 32nm Technology using Forced Stack Technique

As silicon semiconductor device feature size scales down to the nanometer range, planar bulk CMOS design and fabrication encounter significant challenges nowadays. Carbon Nanotube Field Effect Transistor (CNTFET) has been introduced for high stability, high performance and low power SRAM cell design as an alternative material. Technology scaling demands a decrease in both VDD and VT to sustain historical delay reduction, while restraining active power dissipation. Scaling of VT however leads to substantial increase in the sub-threshold leakage power and is expected to become a considerable constituent of the total dissipated power. It has been observed that the stacking of two off devices has smaller leakage current than one off device. This paper proposes a SRAM cell circuit based on CNTFET that uses Forced Stack Technique to reduce leakage power. This circuit is simulated using HSPICE with Stanford CNFET model at 32nm. The simulated results shows that this proposed Forced Stack CNTFET SRAM cell reduces a leakagepower by 38.6% compared to conventional 6T CNTFET SRAM cell with minimal Area and delay trade off.